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cy7c53150, cy7c53120 neuron chip network processor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-10001 rev. *j revised march 20, 2014 features three 8-bit pipelined processors for concurrent processing of application code and network traffic 11-pin i/o port programmable in 34 modes for fast application program development two 16-bit timer/counters for measuring and generating i/o device waveforms 5-pin communication port that supports direct connect and network transceiver interfaces programmable pull-ups on i/o4?i/o 7 and 20 ma sink current on i/o0?i/o3 unique 48-bit id number in every device to facilitate network installation and management low operating current; sleep mode operation for reduced current consumption [1] 0.35 ? m flash process technology 5.0 v operation on-chip lvd circuit to prevent nonvolatile memory corruption during voltage drops 2,048 bytes of sram for buffering network data, system, and application data storage 512 bytes (cy7c53150), 2048 bytes (cy7c53120e2), 4096 bytes (cy7c53120e4) of flash memory with on-chip charge pump for flexible storage of configuration data and application code addresses up to 58 kb of external memory (cy7c53150) 10 kb (cy7c53120e2), 12 kb (cy7c53120e4) of rom containing lontalk network protocol firmware maximum input clock operation of 20 mhz (cy7c53150), 10 mhz (cy7c53120e2), 40 mhz (cy7c53120e4) over a ?40c to 85c [2] temperature range 64-pin tqfp package (cy7c53150) 32-pin soic or 44-pin tqfp package (cy7c53120) media access control processor network processor application processor 2 kb ram communications port i/o block 2 timer/ counters oscillator, clock, and rom internal data bus (0:7) address bus (0:15) control internal cp4 cp0 i/o10 i/o0 clk1 clk2 service reset external address/data bus flash (cy7c53150) (cy7c53120) logic block diagram notes 1. rare combinations of wake-up events occurring during t he go to sleep sequence could pr oduce unexpected sleep behavior. 2. maximum junction temperature is 105 c. t junction = t ambient + v?i? ? ja . 32-pin soic ? ja = 51 c/w. 44-pin tqfp ? ja = 43 c/w. 64-pin tqfp ? ja = 44 c/w.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 2 of 19 contents functional description ..................................................... 3 pin configurations ........................................................... 4 pin descriptions ............................................................... 6 memory usage .................................................................. 7 flash memory retention and endurance ....................... 7 40 mhz 3120 operation .................................................... 7 low voltage inhibit operation ......................................... 7 communications port ...................................................... 7 programmable hysteresis values ............................... 8 programmable glitch filter values [7] ........................... 8 receiver [8] (end-to-end) absolute asymmetry ........... 8 differential receiver (end-to-end) absolute symmetry [9, 10] ..................................................... 8 electrical characteristics ................................................. 9 lvi trip point (v dd) ........................................................... 9 external memory interface timing ? cy7c53150 ....... 10 differential transceiver electri cal characteristics ...... 10 ordering information[23] ............................................... 14 ordering code definitions ..... .................................... 14 package diagrams .......................................................... 15 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc? solutions ...................................................... 19 cypress developer community ................................. 19 technical support ................. .................................... 19
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 3 of 19 functional description the cy7c531x0 neuron chip implements a node for lonworks distributed intelligent control ne tworks. it incorporates, on a single chip, the necessary communication and control functions, both in hardware and firmware, that facilitate the design of a lonworks node. the cy7c531x0 contains a very flexible 5-pin communication port that can be configured to interface with a wide variety of media transceivers at a wide range of data rates. the most common transceiver types are twisted-pair, powerline, rf, ir, fiber-optics, and coaxial. the cy7c531x0 is manufactured using state of the art 0.35 ? m flash technology, providing to designers the most cost-effective neuron chip solution. services at every layer of th e osi networking reference model are implemented in the lontalk firmware based protocol stored in 10-kb rom (cy7c53120e2), 12-kb rom (cy7c53120e4), or off-chip memory (cy7c53150). the firmware also contains 34 preprogrammed i/o drivers, greatly simplifying application programming. the application prog ram is stored in the flash memory (cy7c53120) and/or off-chip memory (cy7c53150), and may be updated by downloading over the network. the cy7c53150 incorporates an external memory interface that can address up to 64 kb with 6 kb of the address space mapped internally. lonworks nodes that require large application programs can take advantage of this external memory capability. the cy7c53150 neuron chip is an exact replacement for the motorola mc143150bx and toshiba tmpn3150b1 devices. the cy7c53120e2 neuron chip is an exact replacement for the motorola mc143120e2 device since it contains the same firmware in rom.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 4 of 19 pin configurations figure 1. 64-pin tqfp pinout 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 nc [4] service v ss v dd v ss v dd clk2 clk1 v ss v dd nc [4] cp0 cp1 cp2 cp3 cp4 a15 e r/w d0 d1 v dd v dd v ss d2 d3 d4 d5 d6 d7 i/o0 i/o1 i/o2 i/o3 reset v pp i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 v dd nc [4] v dd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 v ss cy7c53150-20ai pin 1 indicator [3] nc [4] nc [4] notes 3. the smaller dimple at the bottom left of the marking indicates pin 1. 4. no connect (nc) ? must not be used. (these pins may be used for internal testing.)
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 5 of 19 figure 2. 32-pin soic pinout and 44-pin qfp pinout pin configurations (continued) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd v ss i/o5 i/o6 i/o7 i/o8 i/o9 v dd i/o10 v ss cp4 cp3 cp1 cp0 v dd cp2 reset v dd i/o4 i/o3 i/o2 i/o1 i/o0 service v ss v pp v dd v dd v ss clk2 clk1 v ss nc [4] i/o6 i/o5 v ss v dd nc [4] reset v dd i/o4 i/o3 nc [4] nc [4] cp1 cp0 v dd cp2 nc [4] v ss clk1 clk2 v ss nc [4] 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 pin 1 indicator nc [4] i/o7 i/o8 i/o9 v dd nc [4] i/o10 v ss cp4 cp3 nc [4] nc [4] i/o2 i/o1 i/o0 service nc [4] v ss v pp v dd v dd nc [4] cy7c53120ex-yyai cy7c53120ex-yysi
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 6 of 19 pin descriptions pin name i/o pin function cy7c53150 tqfp-64 pin no. cy7c53120xx soic-32 pin no. cy7c53120xx tqfp-44 pin no. clk1 input oscillator connection or external clock input . 24 15 15 clk2 output oscillator connection . leave open when external clock is input to clk1. maximum of one external load. 23 14 14 reset i/o (built-in pull up) reset pin (active low) . note the allowable external capacitance connected to the reset pin is 100?1000 pf. 6140 service i/o (built-in configurable pull up) service pin (active low) . alternates between input and output at a 76-hz rate. 17 8 5 i/o0?i/o3 i/o large current-sink capacity (20 ma) . general i/o port. the output of timer/ counter 1 may be routed to i/o0. the output of timer/counter 2 may be routed to i/o1. 2, 3, 4, 5 7, 6, 5, 4 4, 3, 2, 43 i/o4?i/o7 i/o (built-in configurable pull ups) general i/o port . the input to timer/counter 1 may be derived from one of i/o4?i/o7. the input to timer/counter 2 may be derived from i/o4. 10, 11, 12, 13 3, 30, 29, 28 42, 36, 35, 32 i/o8?i/o1 0 i/o general i/o port . may be used for serial communication under firmware control. 14, 15, 16 27, 26, 24 31, 30, 27 d0?d7 i/o bidirectional memory data bus . 43, 42, 38, 37, 36, 35, 34, 33 n/a n/a r/w output read/write control output for external memory . 45 n/a n/a e output enable clock control output for external memory . 46 n/a n/a a0?a15 output memory address output port . 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 47 n/a n/a v dd input power input (5 v nom) . all v dd pins must be connected together externally. 7, 20, 22, 26, 40, 41, 44 2, 11, 12, 18, 25, 32 9, 10, 19, 29, 38, 41 v ss input power input (0 v, gnd) . all v ss pins must be connected together externally. 8,19, 21, 25, 39 9, 13, 16, 23, 31 7,13, 16, 26, 37 vpp input in-circuit test mode control . if vpp is high when reset is asserted, the i/o, address and data buses become hi-z. 9108 cp0?cp4 communication network interface bidirectional port supporting communi- cations in three modes . 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24, 25 nc ? no connect . must not be connected on the user?s pc board, since they may be connected internal to the chip. 1, 18, 27, 48, 49 n/a 1, 6, 11, 12, 17, 22, 23, 28, 33, 34, 39, 44
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 7 of 19 memory usage all neuron chips require system firmware to be present when they are powered up. in the case of the cy7c53120 family, this firmware is preprogrammed in the factory in an on-chip rom. in the case of the cy7c53150, the system firmware must be present in the first 16 kb of an off-chip nonvolatile memory such as flash, eprom, eeprom, or nvram. these devices must be programmed in a device programmer before board assembly. because the system firmware impl ements the network protocol, it cannot itself be downloaded over the network. for the cy7c53120 family, the user application program is stored in on-chip flash memory . it may be programmed using a device programmer before board assembly, or may be downloaded and updated over the lontalk network from an external network management tool. for the cy7c53150, the user appl ication program is stored in on-chip flash memory and also in off-chip memory. the user program may initially be programmed into the off-chip memory device using a device programmer. flash memory rete ntion and endurance data and code stored in flash memory is guaranteed to be retained for at least 10 years for programming temperature range of ?25c to 85c. the flash memory can typically be written 100,000 times without any data loss. [5] an erase/write cycle takes 20 ms. the system firmware extends the effective endurance of flash memory in two ways. if the data being written to a byte of flash memory is the same as the data already pr esent in that byte, the firmware does not perform the physical write. so for example, an appli- cation that sets its own address in flash memory after every reset does not use up any write cycles if the address has not changed. in addition , system firmware version 13.1 or higher is able to aggregate writes to eight successive address locations into a single write for cy7c53120e4 devices. for example, if 4 kb of code is downloaded over the network, the firmware would execute only 512 writes rather than 4,096. 40 mhz 3120 operation the cy7c53120e4-40 device was designed to run at frequencies up to 40 mhz using an external clock oscillator. it is important to note that external oscillators may typically take on the order of 5 ms to stabilize after power-up. the neuron chip must be held in reset until the clk1 input is stable. with some oscillators, this may require the use of a reset-stretching low-voltage detection chip/circuit . check the oscillator vendor?s specification for more information about start-up stabilization times. low voltage inhibit operation the on-chip low-voltage inhibit circuit trips the neuron chip whenever the v dd input is less than 4.1 0.3 v. this feature prevents the corruption of nonvolatile memory during voltage drops. communications port the neuron chip includes a versatile 5-pin communications port that can be configured in three different ways. in single-ended mode, pin cp0 is used for receiving serial data, pin cp1 for trans- mitting serial data, and pin cp2 enables an external transceiver. data is communicated using differential manchester encoding. in special purpose mode, pin cp0 is used for receiving serial data, pin cp1 for transmitting serial data, pin cp2 transmits a bit clock, and pin cp4 transmits a frame clock for use by an external intelligent transceiver. in this mode, the external transceiver is responsible for encoding and decoding the data stream. in differential mode, pins cp0 and cp1 form a differential receiver with built-in programm able hysteresis and low pass filtering. pins cp2 and cp3 form a differential driver. serial data is communicated using differential manchester encoding. the following tables describe the communications port when used in differential mode. note 5. for detailed information about data retention afte r 100k cycles, see the cypre ss qualification report.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 8 of 19 programmable hysteresis values (expressed as differential peak-to-peak voltages in terms of v dd ) hysteresis [6] v hys min v hys typ v hys max 0 0.019 v dd 0.027 v dd 0.035 v dd 1 0.040 v dd 0.054 v dd 0.068 v dd 2 0.061 v dd 0.081 v dd 0.101 v dd 3 0.081 v dd 0.108 v dd 0.135 v dd 4 0.101 v dd 0.135 v dd 0.169 v dd 5 0.121 v dd 0.162 v dd 0.203 v dd 6 0.142 v dd 0.189 v dd 0.236 v dd 7 0.162 v dd 0.216 v dd 0.270 v dd programmable glitch filter values [7] (receiver (end-to-end) filter values expressed as transient pulse suppression times) filter (f) min typ max unit 0 10 75 140 ns 1 120 410 700 ns 2 240 800 1350 ns 3 480 1500 2600 ns receiver [8] (end-to-end) absolute asymmetry (worst case across hysteresis) filter (f) max (t plh ? t phl ) unit 0 35 ns 1 150 ns 2 250 ns 3 400 ns differential receiver (end-to-end) absolute symmetry [9, 10] filter (f) hysteresis (h) max (t plh ? t phl ) unit 0 0 24 ns cp0 ? 3 ns cp1 v dd /2 ? cp0 ? cp1 ? ? v hys + 200 mv figure 3. receiver input waveform notes 6. hysteresis values are on the condition that the input signal swing is 200 mv greater than the programmed value. 7. must be disabled if data rate is 1.25 mbps or greater. 8. receiver input, v d = v cp0 ? v cp1 , at least 200 mv greater than hysteresis levels. see figure 3 . 9. cpo and cp1 inputs each 0.60 vp ? p, 1.25 mhz sine wave 180 out of phase with each other as shown in figure 10 . v dd = 5.00 v 5%. 10. t plh : time from input switching states from low to high to output switching states. t phl : time from input switching states from high to low to output switching states.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 9 of 19 electrical characteristics (v dd = 4.5 v?5.5 v) parameter description min typ max unit v il input low voltage i/o0?i/o10, cp0, cp3, cp4, service , d0-d7, reset cp0, cp1 (differential) ? ? ? ? 0.8 programmable v v ih input high voltage i/o0?i/o10, cp0, cp3, cp4, service , d0-d7, reset cp0, cp1 (differential) 2.0 programmable ? ? ? ? v v ol low-level output voltage i out < 20 ? a standard outputs (i/o l = 1.4 ma) [11] high sink (i/o0?i/o3), service , reset (i ol = 20 ma) high sink (i/o0?i/o3), service , reset (i ol = 10 ma) maximum sink (cp2, cp3) (i ol = 40 ma) maximum sink (cp2, cp3) (i ol = 15 ma) ? ? ? ? ? ? ? ? ? ? ? ? 0.1 0.4 0.8 0.4 1.0 0.4 v v oh high-level output voltage i out < 20 ? a standard outputs (i oh = ?1.4 ma) [11] high sink (i/o0 ? i/o3), service (i oh = ?1.4 ma) maximum source (cp2, cp3) (i oh = ?40 ma) maximum source (cp2, cp3) (i oh = ?15 ma) v dd ? 0.1 v dd ? 0.4 v dd ? 0.4 v dd ? 1.0 v dd ? 0.4 ? ? ? ? ? ? ? ? ? ? v v hys hysteresis (excluding clk1) 175 ? ? mv i in input current (excluding pull ups) (v ss to v dd ) [12] ??10 ? a i pu pull up source current (v out = 0 v, output = high-z) [12] 60 ? 260 ? a i dd operating mode supply current [13] 40-mhz clock [14] 20-mhz clock 10-mhz clock 5-mhz clock 2.5-mhz clock 1.25-mhz clock 0.625-mhz clock [14] ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55 32 20 12 8 7 3 ma i ddsleep sleep mode supply current [1, 13] ? ? 100 ? a lvi trip point (v dd ) part number min typ max unit cy7c53120e2, cy7c53120e4, and cy7c53150 3.8 4.1 4.4 v notes 11. standard outputs are i/o4?i/o10, cp0, cp1, and cp4. (reset is an open drain input/output. clk2 must have < 15 pf load.) for cy7c53150, standard outputs also include a0?a15, d0?d7, e , and r/w. 12. i/o4?i/o7 and service have configurable pull ups. reset has a permanent pull up. 13. supply current measurement conditions: v dd = 5 v, all outputs under no-load conditions, all inputs < 0.2 v or ? (v dd ? 0.2 v), configurable pull ups off, crystal oscillator clock input, differential receiver disabled. the differential rece iver adds approximately 200 a typical and 600 a maximum whe n enabled. it is enabled on either of the following conditions: ? neuron chip in operating mode and comm port in differential mode. ? neuron chip in sleep mode and comm port in differential mode and comm port wake-up not masked. 14. supported through an external oscillator only.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 10 of 19 external memory inte rface timing ? cy7c53150 v dd 10% (v dd = 4.5 v to 5.5 v, t a = ?40 c to +85 c [2] ) parameter description min max unit t cyc memory cycle time (system clock period) [15] 100 3200 ns pw eh pulse width, e high [16] t cyc /2 ? 5 t cyc /2 + 5 ns pw el pulse width, e low [16] t cyc /2 ? 5 t cyc /2 + 5 ns t ad delay, e high to address valid [20] ? 35 ns t ah address hold time after e high [20] 10 ? ns t rd delay, e high to r/w valid read [20] ? 25 ns t rh r/w hold time read after e high 5 ? ns t wr delay, e high to r/w valid write ? 25 ns t wh r/w hold time write after e high 5 ? ns t dsr read data setup time to e high 15 ? ns t dhr data hold time read after e high 0 ? ns t dhw data hold time write after e high [17, 18] 10 ? ns t ddw delay, e low to data valid ? 12 ns t dhz data three state hold time after e low [19] 0 ? ns t ddz delay, e high to data three-state [18] ? 42 ns t acc external memory access time (t acc = t cyc ? t ad ? t dsr ) at 20-mhz input clock 50 ? ns differential transceiver electrical characteristics characteristic min max unit receiver common mode voltage range to maintain hysteresis [21] 1.2 v dd ? 2.2 v receiver common mode range to operate with unspecified hysteresis 0.9 v dd ? 1.75 v input offset voltage ?0.05 v hys ? 35 0.05 v hys + 35 mv propagation delay (f = 0, v id = v hys /2 + 200 mv) ? 230 ns ns input resistance 5 ? m ? wake-up time ? 10 ? s differential output impedance for cp2 and cp3 [22] 35 ? notes 15. t cyc = 2(1/f), where f is the input clock (clk1) fr equency (20, 10, 5, 2.5, 1.25, or 0.625 mhz). 16. refer to figure 5 for detailed measurement information. 17. the data hold parameter, t dhw , is measured to the disable levels shown in figure 7 , rather than to the traditional data invalid levels. 18. refer to figure 8 and figure 7 for detailed measurement information. 19. the three-state condition is when the device is not actively driving data. refer to figure 4 and figure 7 for detailed measurement information. 20. to meet the timing above for 20-mhz operation, the loading on a0?a15, d0?d7, and r/w is 30 pf. loading on e is 20 pf. 21. common mode voltage is defined as the average value of the waveform at each input at the time switching occurs. 22. z 0 = |v[cp2]-v[cp3] |/40 ma for 4.75 < v dd < 5.25 v.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 11 of 19 figure 4. signal loading for timing sp ecifications unless otherwise specified figure 5. test point levels for e pulse width measurements figure 6. drive levels and test point levels fo r timing specifications unless otherwise specified figure 7. test point levels for driven-to-three-state time measurements figure 8. signal loading for dr iven-to-three-state time measurements test signal c l c l = 20 pf for e c l = 30 pf for a0?a15, d0?d7, and r/w c l = 50 pf for all other signals pw el 2.0 v pw eh 2.0 v 0.8 v drive to 2.4 v drive to 0.4 v 2.0 v 0.8 v b a 2.0 v 0.8 v a ? signal valid-to-sig nal valid specification (maximum or minimum) b ? signal valid-to-signal invalid specification (maximum or minimum) v ol + 0.5 v v oh ? 0.5 v v oh ? measured high output drive level v ol ? measured low output drive level test signal c l = 30 pf i load = 1.4 ma v dd /2
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 12 of 19 figure 9. external memory interface timing diagram memory read memory write memory write memory read data (out) 30 pf load data (in) r/w 30 pf load 30 pf load (a0 ? a15) e 20 pf load t dsr t dhr t dsr t cyc t ddw t rd t rh t wr pw eh data out address address address address data in address (d0 ? d7) data out data in t dhr (d0 ? d7) t ad t ad t ad t ad t ah t ah t ah t ah t wh pw el t ddw t ddz t dhz t ddz t dhz t dhw t dhw
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 13 of 19 figure 10. differential receiver input hysteresis voltage measurement waveforms -1 1 2 3 4 5 neuron chip's internal comparator 0v 5v voltage time v(cp0) v(cp1) v(cp0)-v(cp1) vh vcm vtrip+ vtrip- common-mode voltage: vcm = ( v(cp0) + v(cp1) ) / 2 hysteresis voltage: vh = [vtrip+] - [vtrip-]
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 14 of 19 ordering code definitions ordering information [23] part number flash (kb) rom (kb) firmware version max input clock (mhz) package name package type cy7c53150-20axi 0.5 0 n/a 20 [24] a64sa 64-pin tqfp cy7c53150-20axit 0.5 0 n/a 20 [24] a64sa 64-pin tqfp ? tape and reel CY7C53120E2-10SXI [25] 2 10 6 10 s32.45 32-pin soic cy7c53120e4-40sxi [26] 4 12 13 40 s32.45 32-pin soic cy7c53120e4-40sxit 4 12 13 40 s32.45 32-pin soic ? tape and reel cy7c53120e4-40axi [26] 4 12 13 40 a44 44-pin tqfp notes 23. all parts contain 2 kb of sram. 24. cy7c53150 may be used with 20-mhz input clock only if th e firmware in external memory is version 13 or later. 25. cy7c53120e2 firmware is bit-for-bit identical with motorola mc143120e2 firmware. 26. cy7c53120e4 requires upgraded lonbuilder? and nodebuilder? software.
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 15 of 19 package diagrams figure 11. 44-pin tqfp (10 10 1.4 mm) package outline, 51-85064 figure 12. 64-pin tqfp (14 14 1.4 mm) package outline, 51-85046 51-85064 *f 51-85046 *f
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 16 of 19 figure 13. 32-pin soic (450 mils) package outline, 51-85081 package diagrams (continued) 51-85081 *e
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 17 of 19 acronyms document conventions units of measure acronym description acronym description ac alternating current lvd low voltage detect cmos complementary metal oxide semiconductor pcb printed circuit board dc direct current psoc ? programmable system-on-chip eeprom electrically erasable programmable read-only memory soic small-outline in tegrated circuit gpio general purpose i/o tqfp thin quad flat pack symbol unit of measure symbol unit of measure c degree celsius ms millisecond hz hertz na nanoampere khz kilohertz ns nanosecond k ? kilohm w ohm mhz megahertz % percent a microampere pf picofarad s microsecond v volts ma milliampere w watt mm millimeter
cy7c53150, cy7c53120 document number: 38-10001 rev. *j page 18 of 19 document history page document title: cy7c53150, cy7c53120, neuron chip network processor document number: 38-10001 revision ecn orig. of change submission date description of change ** 111472 dsg 11/28/01 change from sp ec number: 38-00891 to 38-10001 *a 111990 cfb 02/06/02 changed the max. cur rent values specified the flash endurance of ?100k typical? with reference to qual report fixed some incorrect footnotes and figure numbering *b 114465 kbo 04/24/02 added sleep metastability footnote added junction temperature footnote added maximum sleep current footnote changed ?eeprom? references to ?flash memory? *c 115269 kbo 04/26/02 repositioned note 3 *d 124450 kbo 03/25/03 removed no te 2 regarding data retention removed note 16 regarding max sleep current changed the system ima ge firmware version from v12 to v13.1 *e 837840 boo 3/14/07 modified the ordering informat ion table; added an ?x? to indicate the part numbers are pb-free; two tape-and -reel options are available now. implemented new template. *f 2811866 tge 11/20/2009 updated template. modified note 1 to add reference to the neuron trm. *g 2899886 ved 03/26/10 removed inactive part from the ordering information table. updated package diagrams. updated links in sales, solutions and legal information. *h 3271364 reid / njf / uvs / pkar 06/01/11 updated ordering information table: firmware version for the following parts changed from 12 to 13. cy7c53120e4-40sxi cy7c53120e4-40sxit cy7c53120e4-40axi added ordering code definitions added acronyms, and units of measure. revised package diagram specs 51-85064 and 51-85046 to *e. *i 3540297 gnkk 03/02/2012 sunset review; no content updates. *j 4313266 pmad 03/20/2014 updated features : updated note 1. updated package diagrams : spec 51-85064 ? changed revision from *e to *f. spec 51-85046 ? changed revision from *e to *f. spec 51-85081 ? changed revision from *d to *e. updated in new template.
document number: 38-10001 rev. *j revised march 20, 2014 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c53150, cy7c53120 ? cypress semiconductor corporation, 2001-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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